View UPD78P4908_96365.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATA SHEET
MOS INTEGRATED CIRCUIT
PD78P4908
16-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The PD78P4908, 78K/IV series' product, is a one-time PROM version of the PD784907 and PD784908 with internal mask ROM. Since user programs can be written to PROM, this microcomputer is best suited for evaluation in system development, manufacture of small quantities of multiple products, and fast start-up of applications. For specific functions and other detailed information, consult the following user's manuals. These manuals are required reading for design work. PD784908 Subseries User's Manual - Hardware : U11787E 78K/IV Series User's Manual - Instruction : U10905E
FEATURES
* * * *
78K/IV series Internal PROM: 128 Kbytes Internal RAM: 4,352 bytes Supply voltage: VDD = 4.5 to 5.5 V (At main clock: fXX = 12.58 MHz, internal system clock = fXX: fCYK = 79 ns) VDD = 4.0 to 5.5 V (Other than above: fCYK = 159 ns)
ORDERING INFORMATION
Part number Package 100-pin plastic QFP (14 x 20 mm) Internal ROM One-time PROM
PD78P4908GF-3BA
The information in this document is subject to change without notice. Document No. U11681EJ2V0DS00 (2nd edition) Date Published February 1999 N CP(K) Printed in Japan
The mark
shows major revised points.
(c)
1996
PD78P4908
78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM
: Under mass production : Under development
I2C bus supported
Multimaster I2C bus supported
PD784038Y
Standard models
PD784225Y PD784225
80 pins, added ROM correction Multimaster I2C bus supported
PD784038
Enhanced internal memory capacity, pin compatible with the PD784026 Multimaster I2C bus supported
PD784026
Enhanced A/D, 16-bit timer, and power management
PD784216Y PD784216
100 pins, enhanced I/O and internal memory capacity
PD784218Y PD784218
Enhanced internal memory capacity, added ROM correction
PD784054 PD784046
ASSP models Equipped with 10-bit A/D
PD784955
For DC inverter control
PD784938 PD784908
Equipped with IEBus controller
TM
Enhanced function of the PD784908, enhanced internal memory capacity, added ROM correction
Multimaster I2C bus supported
PD784928Y PD784928 PD784915
For software servo control, equipped with analog circuit for VCR, enhanced timer Enhanced function of the PD784915
2
Data Sheet U11681EJ2V0DS00
PD78P4908
FUNCTIONS
(1/2)
Item Number of basic instructions (mnemonics) General-purpose register Minimum instruction execution time Internal memory Memory space I/O ports Total Input Input/output Additional function pinsNote LED direct drive outputs Transistor direct drive N-ch open drain Real-time output ports IEBus controller Timer/counter ROM RAM 113 Function
8 bits x 16 registers x 8 banks, or 16 bits x 8 registers x 8 banks (memory mapping)
* 320 ns/636 ns/1.27 s/2.54 s (at 6.29 MHz) * 160 ns/320 ns/636 ns/1.27 s (at 12.58 MHz)
128 Kbytes 4,352 bytes Program and data: 1 Mbyte 80 8 72 24
8
4 4 bits x 2, or 8 bits x 1 Incorporated (simple version) Timer/counter 0: (16 bits) Timer register x 1 Capture register x 1 Compare register x 2 Timer register x 1 Capture register x 1 Capture/compare register x 1 Compare register x 1 Timer register x 1 Capture register x 1 Capture/compare register x 1 Compare register x 1 Timer register x 1 Compare register x 1 Pulse output capability * Toggle output * PWM/PPG output * One-shot pulse output Real-time output port
Timer/counter 1: (16 bits)
Timer/counter 2: (16 bits)
Pulse output capability * Toggle output * PWM/PPG output
Timer 3: (16 bits) Clock timer
Interrupt requests are generated at 0.5-second intervals. (A clock timer oscillator is incorporated.) Either the main clock (6.29 MHz/12.58 MHz) or real-time clock (32.768 kHz) can be selected as the input clock. Selected from fCLK, fCLK/2, fCLK/4, fCLK/8, or fCLK/16 (can be used as a 1-bit output port) 12-bit resolution x 2 channels UART/IOE (3-wire serial I/O) : 2 channels (incorporating baud rate generator) CSI (3-wire serial I/O) : 2 channels
Clock output PWM outputs Serial interface
Note Additional function pins are included in the I/O pins.
Data Sheet U11681EJ2V0DS00
3
PD78P4908
(2/2)
Item A/D converter Watchdog timer Standby Interrupt Hardware source Software source Nonmaskable Maskable 8-bit resolution x 8 channels 1 channel HALT/STOP/IDLE mode 27 (20 internal, 7 external (sampling clock variable input: 1)) BRK or BRKCS instruction, operand error 1 internal, 1 external 19 internal, 6 external Function
* 4-level programmable priority * 3 operation statuses: vectored interrupt, macro service, context switching
Power supply voltage
* VDD = 4.5 to 5.5 V (At main clock: fXX = 12.58 MHz, internal system clock = fXX: fCYK =
79 ns)
* VDD = 4.0 to 5.5 V (Other than above: fCYK = 159 ns)
Package 100-pin plastic QFP (14 x 20 mm)
4
Data Sheet U11681EJ2V0DS00
PD78P4908
CONTENTS
1. 2. 3. 4.
DIFFERENCES BETWEEN PD78P4908 AND MASK ROM PRODUCTS ............................ PIN CONFIGURATION (TOP VIEW) ......................................................................................... BLOCK DIAGRAM ..................................................................................................................... PIN FUNCTIONS ........................................................................................................................
4.1 4.2 PINS FOR NORMAL OPERATING MODE .................................................................................... PINS FOR PROM PROGRAMMING MODE (VPP +5 V or +12.5 V, RESET = L) .................... 4.2.1 4.2.2 4.3 Pin Functions ................................................................................................................. Pin Functions .................................................................................................................
6 7 10 11
11 14 14 15 16
I/O CIRCUITS FOR PINS AND HANDLING OF UNUSED PINS .................................................
5. 6.
INTERNAL MEMORY SIZE SELECT REGISTER (IMS) .......................................................... PROM PROGRAMMING ............................................................................................................
6.1 6.2 6.3 OPERATION MODE ........................................................................................................................ PROM WRITE SEQUENCE ............................................................................................................ PROM READ SEQUENCE .............................................................................................................
19 20
20 22 26
7. 8. 9.
SCREENING ONE-TIME PROM PRODUCTS .......................................................................... ELECTRICAL CHARACTERISTICS ......................................................................................... PACKAGE DRAWING ................................................................................................................
26 27 51 52 53 56 58
10. RECOMMENDED SOLDERING CONDITIONS ........................................................................ APPENDIX A DEVELOPMENT TOOLS.......................................................................................... APPENDIX B CONVERSION SOCKET (EV-9200GF-100) PACKAGE DRAWING ..................... APPENDIX C RELATED DOCUMENTS .........................................................................................
Data Sheet U11681EJ2V0DS00
5
PD78P4908
1. DIFFERENCES BETWEEN PD78P4908 AND MASK ROM PRODUCTS
The PD78P4908 is produced by replacing the mask ROM in the PD784907 or PD784908 with PROM to which data can be written. The functions of the PD78P4908 are the same as those of the PD784907 or PD784908 except for the PROM specification such as writing and verification, except that the PROM size can be changed to 96 or 128 Kbytes, and except that the internal RAM size can be changed to 3,584 or 4,352 bytes. Table 1-1 shows the differences between these products. Table 1-1. Differences Between the PD78P4908 and Mask ROM Products
Product name Item Internal program memory
PD78P4908
PD784907
PD784908
* 128-Kbyte PROM * Can be changed to 96
Kbytes by IMS
* 96-Kbyte mask ROM
* 128-Kbyte mask ROM
Internal RAM
* 4,352-byte internal RAM * Can be changed to 3,584
bytes by IMS
* 3,584-byte internal RAM
* 4,352-byte internal RAM
Pin connection Power supply voltage
Pin functions related to writing or reading of PROM have been added to the PD78P4908.
* VDD = 4.5 to 5.5 V
(At main clock: fXX = 12.58 MHz, internal system clock = fXX: fCYK = 79 ns * VDD = 4.0 to 5.5 V (Other than above: fCYK = 159 ns)
* VDD = 4.0 to 5.5 V
(At main clock: fXX = 12.58 MHz, internal system clock = fXX: fCYK = 79 ns) * VDD = 3.5 to 5.5 V (Other than above: fCYK = 159 ns)
Electrical characteristics
Partially differs between these products.
6
Data Sheet U11681EJ2V0DS00
PD78P4908
2. PIN CONFIGURATION (TOP VIEW)
(1) Normal operation mode
* 100-pin plastic QFP (14 x 20 mm)
PD78P4908GF-3BA
P30/RxD/SI1 P27/SI0 P26/INTP5 P25/INTP4/ASCK/SCK1 P24/INTP3 P23/INTP2/CI P22/INTP1 P21/INTP0 P20/NMI TX RX AVSS AVREF1 AVDD P77/ANI7
P36/TO2 P37/TO3 P100 P101 P102 P103 P104 P105/SCK3 P106/SI3 P107/SO3 RESET XT2 XT1 VSS X2 X1 REGOFFNote 2 REGCNote 3 VDD P00 P01 P02 P03 P04 P05 P06 P07 P67/REFRQ/HLDAK P66/WAIT/HLDRQ P65/WR
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 74 7 73 8 9 72 71 10 70 11 12 69 13 68 14 67 15 66 65 16 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P34/TO0 P33/SO0 P32/SCK0 P31/TxD/SO1
P35/TO1
P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 TESTNote 1 PWM1 PWM0 P17 P16 P15 P14/TxD2/SO2 P13/RxD2/SI2 P12/ASCK2/SCK2 P11 P10 ASTB/CLKOUT P90 P91 P92 P93 P94 P95 P96 P97 P40/AD0 P41/AD1 P42/AD2
P64/RD P63/A19 P62/A18 P61/A17 P60/A16 P57/A15 P56/A14 P55/A13 P54/A12 VSS VDD P53/A11
Notes 1. Connect the TEST pin to VSS directly. 2. Connect the REGOFF pin to VSS directly (select regulator operation) 3. Connect the REGC pin to VSS through a 1-F capacitor.
P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3
Data Sheet U11681EJ2V0DS00
7
PD78P4908
A8-A19 AD0-AD7 ANI0-ANI7 ASTB AVDD AVREF1 AVSS CI CLKOUT HLDAK HLDRQ NMI P00-P07 P10-P17 P20-P27 P30-P37 P40-P47 P50-P57 P60-P67 P70-P77 P90-P97 P100-P107 : Address bus : Address/data bus : Analog input : Address strobe : Analog power supply : Reference voltage : Analog ground : Clock input : Clock output : Hold acknowledge : Hold request : Non-maskable interrupt : Port 0 : Port 1 : Port 2 : Port 3 : Port 4 : Port 5 : Port 6 : Port 7 : Port 9 : Port 10 PWM0, PWM1 : Pulse width modulation output RD REFRQ REGC REGOFF RESET RX RxD, RxD2 SCK0-SCK3 SI0-SI3 SO0-SO3 TEST TO0-TO3 TX TxD, TxD2 VDD VSS WAIT WR X1, X2 XT1, XT2 : Read strobe : Refresh request : Regulator capacitance : Regulator off : Reset : IEBus receive data : Receive data : Serial clock : Serial input : Serial output : Test : Timer output : IEBus transmit data : Transmit data : Power supply : Ground : Wait : Write strobe : Crystal (main system clock) : Crystal (watch)
ASCK, ASCK2 : Asynchronous serial clock
INTP0-INTP5 : Interrupt from peripherals
8
Data Sheet U11681EJ2V0DS00
PD78P4908
(2) PROM programming mode
* 100-pin plastic QFP (14 x 20 mm)
PD78P4908GF-3BA
OPEN (L) A9 VSS OPEN OPEN VSS VSS VDD OPEN
OPEN
RESET OPEN VSS VSS OPEN VSS VDD D0 D1 D2 D3 D4 D5 D6 D7 (L) PGM CE
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VSS
OPEN
VPP
OPEN
A0 A1 A2
A15 A14 A13 A12 VSS
OE
VDD A11 A10 A16 A8 A7
A6 A5
Caution L VSS
: Connect these pins separately to the VSS pins through 10-k pull-down resistors. : To be connected to the ground.
Open : Nothing should be connected on these pins. RESET: Set a low-level input. A0-A16 CE D0-D7 OE PGM : Address bus : Chip enable : Data bus : Output enable : Program RESET VDD VPP VSS : Reset : Power supply : Programming power supply : Ground
(L)
A4 A3
Data Sheet U11681EJ2V0DS00
9
PD78P4908
3. BLOCK DIAGRAM
NMI INTP0-INTP5 INTP3 TO0 TO1 UART/IOE2 Baud-rate generator UART/IOE1 Baud-rate generator RxD/SI1 TxD/SO1 ASCK/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2 SCK0 Clocked serial interface 78K /IV CPU core
(RAM 512 bytes)
Programmable interrupt controller
Timer/counter 0 (16 bits)
INTP0
Timer/counter 1 (16 bits)
SO0 SI0
INTP1 INTP2/CI TO2 TO3
Timer/counter 2 (16 bits)
ROM
(128 Kbytes)
SCK3 Clocked serial interface 3 SO3 SI3 ASTB /CLKOUT AD0-AD7 A8-A15 A16-A19 RD WR WAIT/HLDRQ REFRQ/HLDAK D0-D7Note A0-A16Note CENote OENote PGMNote P00-P07 P10-P17 P20-P27 P30-P37 P40-P47 P50-P57 P60-P67 P70-P77 P90-P97 P100-P107
Timer 3 (16 bits) P00-P03 Real-time output port P04-P07
Clock output
Bus interface PWM0 PWM PWM1 ANI0-ANI7 AVDD AVREF1 AVSS INTP5 TX IEBus controller RX RESET TEST X1 X2 REGC REGOFF VPPNote VDD VSS XT1 Watch timer XT2 A /D converter Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 System control (regulator) Port 7 Watchdog timer Port 9 Port 10 RAM
(3,840 bytes)
Note In the PROM programming mode.
10
Data Sheet U11681EJ2V0DS00
PD78P4908
4. PIN FUNCTIONS
4.1 PINS FOR NORMAL OPERATING MODE
(1) Port pins (1/2)
Pin P00-P07 I/O I/O Also used as -- Function Port 0 (P0): * 8-bit I/O port. * Functions as a real-time output port (4 bits x 2). * Inputs and outputs can be specified bit by bit. * The use of built-in pull-up resistors can be simultaneously specified by software for all pins in input mode. * Can drive a transistor. Port 1 (P1): * 8-bit I/O port. * Inputs and outputs can be specified bit by bit. * The use of built-in pull-up resistors can be simultaneously specified by software for all pins in input mode. * Can drive LED.
P10 P11 P12 P13 P14 P15-P17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34-P37 P40-P47
I/O
-- -- ASCK2/SCK2 RxD2/SI2 TxD2/SO2 --
Input
NMI INTP0 INTP1 INTP2/CI INTP3 INTP4/ASCK/SCK1 INTP5 SI0
Port 2 (P2): * 8-bit input-only port. * P20 does not function as a general-purpose port (nonmaskable interrupt). However, the input level can be checked by an interrupt service routine. * The use of built-in pull-up resistors can be specified by software for pins P22 to P27 (in units of 6 bits). * The P25/INTP4/ASCK/SCK1 pin functions as the SCK1 input/output pin by CSIM1.
I/O
RxD/SI1 TxD/SO1 SCK0 SO0 TO0-TO3
Port 3 (P3): * 8-bit I/O port. * Inputs and outputs can be specified bit by bit. * The use of built-in pull-up resistors can be simultaneously specified by software for all pins in input mode. * P32 and P33 can be set as the N-ch open-drain pin. Port 4 (P4): * 8-bit I/O port. * Inputs and outputs can be specified bit by bit. * The use of built-in pull-up resistors can be simultaneously specified by software for all pins in input mode. * Can drive LED.
I/O
AD0-AD7
Data Sheet U11681EJ2V0DS00
11
PD78P4908
(1) Port pins (2/2)
Pin P50-P57 I/O I/O Also used as A8-A15 Function Port 5 (P5): * 8-bit I/O port. * Inputs and outputs can be specified bit by bit. * The use of built-in pull-up resistors can be simultaneously specified by software for all pins in input mode. * Can drive LED. Port 6 (P6): * 8-bit I/O port. * Inputs and outputs can be specified bit by bit. * The use of built-in pull-up resistors can be simultaneously specified by software for all pins in input mode.
P60-P63 P64 P65 P66 P67 P70-P77
I/O
A16-A19 RD WR WAIT/HLDRQ REFRQ/HLDAK
I/O
ANI0-ANI7
Port 7 (P7): * 8-bit I/O port. * Inputs and outputs can be specified bit by bit. Port 9 (P9): * 8-bit I/O port. * Inputs and outputs can be specified bit by bit. * The use of built-in pull-up resistors can be simultaneously specified by software for all pins in input mode. Port 10 (P10): * 8-bit I/O port. * Inputs and outputs can be specified bit by bit. * The use of built-in pull-up resistors can be simultaneously specified by software for all pins in input mode. * P105 and P107 can be set as the N-ch open-drain pin.
P90-P97
I/O
--
P100-P104 P105 P106 P107
I/O SCK3 SI3 SO3
--
12
Data Sheet U11681EJ2V0DS00
PD78P4908
(2) Non-port pins (1/2)
Pin TO0-TO3 CI RxD RxD2 TxD TxD2 ASCK ASCK2 SI0 SI1 SI2 SI3 SO0 SO1 SO2 SO3 SCK0 SCK1 SCK2 SCK3 NMI INTP0 Input I/O Output Input Input Output I/O Output Input Input Also used as P34-P37 P23/INTP2 P30/SI1 P13/SI2 P31/SO1 P14/SO2 P25/INTP4/SCK1 P12/SCK2 P27 P30/RxD P13/RxD2 P106 P33 P31/TxD P14/TxD2 P107 P32 P25/INTP4/ASCK P12/ASCK2 P105 P20 P21 Timer output Input of a count clock for timer/counter 2 Serial data input (UART0) Serial data input (UART2) Serial data output (UART0) Serial data output (UART2) Baud rate clock input (UART0) Baud rate clock input (UART2) Serial data input (3-wire serial I/O 0) Serial data input (3-wire serial I/O 1) Serial data input (3-wire serial I/O 2) Serial data input (3-wire serial I/O 3) Serial data output (3-wire serial I/O 0) Serial data output (3-wire serial I/O 1) Serial data output (3-wire serial I/O 2) Serial data output (3-wire serial I/O 3) Serial clock I/O (3-wire serial I/O 0) Serial clock I/O (3-wire serial I/O 1) Serial clock I/O (3-wire serial I/O 2) Serial clock I/O (3-wire serial I/O 3) External interrupt request -- * Input of a count clock for timer/counter 1 * Capture/trigger signal for CR11 or CR12 * Input of a count clock for timer/counter 2 * Capture/trigger signal for CR22 * Input of a count clock for timer/counter 2 * Capture/trigger signal for CR21 * Input of a count clock for timer/counter 0 * Capture/trigger signal for CR02 -- Input of a conversion start trigger for A/D converter Time multiplexing address/data bus (for connecting external memory) High-order address bus (for connecting external memory) High-order address during address expansion (for connecting external memory) Strobe signal output for reading the contents of external memory Strobe signal output for writing on external memory Wait signal insertion Refresh pulse output to external pseudo static memory Input of bus hold request Output of bus hold response Latch timing output of time multiplexing address (A0-A7) (for connecting external memory) Function
INTP1
P22
INTP2
P23/CI
INTP3
P24
INTP4 INTP5 AD0-AD7 A8-A15 A16-A19 RD WR WAIT REFRQ HLDRQ HLDAK ASTB I/O Output Output Output Output Input Output Input Output Output
P25/ASCK/SCK1 P26 P40-P47 P50-P57 P60-P63 P64 P65 P66/HLDRQ P67/HLDAK P66/WAIT P67/REFRQ CLKOUT
Data Sheet U11681EJ2V0DS00
13
PD78P4908
(2) Non-port pins (2/2)
Pin CLKOUT PWM0 PWM1 RX TX REGC I/O Output Output Output Input Output -- Also used as ASTB -- -- -- -- -- Clock output PWM output 0 PWM output 1 Data input (IEBus) Data output (IEBus) Capacitor connection for stabilizing the regulator output/Power supply when the regulator is stopped. Connect to VSS via a 1-F capacitor. Signal for specifying regulator operation. Directly connect to VSS (regulator selected). Chip reset Crystal input for system clock oscillation (A clock pulse can also be input to the X1 pin.) Real-time clock connection Function
REGOFF
--
--
RESET X1 X2 XT1 XT2 ANI0-ANI7 AVREF1 AVDD AVSS VDD VSS TEST
Input Input -- Input -- Input -- P70-P77
-- --
-- --
Analog voltage inputs for the A/D converter -- Application of A/D converter reference voltage Positive power supply for the A/D converter Ground for the A/D converter Positive power supply Ground
Input
Directly connect to VSS. (The TEST pin is for the IC test.)
4.2
PINS FOR PROM PROGRAMMING MODE (VPP +5 V or +12.5 V, RESET = L)
4.2.1 Pin Functions
Pin name VPP I/O -- Function PROM programming mode selection High voltage input during program write or verification PROM programming mode selection Address bus I/O Input Data bus PROM enable input/program pulse input Read strobe input to PROM Program/program inhibit input during PROM programming mode -- -- Positive power supply GND
RESET A0-A16 D0-D7 CE OE PGM VDD VSS
Input
14
Data Sheet U11681EJ2V0DS00
PD78P4908
4.2.2 Pin Functions
(1) VPP (Programming power supply): Input Input pin for setting the PD78P4908 to the PROM programming mode. When the input voltage on this pin is +6.5 V or more and when RESET input goes low, the PD78P4908 enters the PROM programming mode. When CE is made low for VPP = +12.5 V and OE = high, program data on D0 to D7 can be written into the internal PROM cell selected by A0 to A16. (2) RESET (Reset): Input Input pin for setting the PD78P4908 to the PROM programming mode. When input on this pin is low, and when the input voltage on the VPP pin goes +5 V or more, the PD78P4908 enters the PROM programming mode. (3) A0 to A16 (Address bus): Input Address bus that selects an internal PROM address (0000H to 1FFFFH) (4) D0 to D7 (Data bus): I/O Data bus through which a program is written on or read from internal PROM (5) CE (Chip enable): Input This pin inputs the enable signal from internal PROM. When this signal is active, a program can be written or read. (6) OE (Output enable): Input This pin inputs the read strobe signal to internal PROM. When this signal is made active for CE = low, a onebyte program in the internal PROM cell selected by A0 to A16 can be read onto D0 to D7. (7) PGM (Program): Input The input pin for the operation mode control signal of the internal PROM. Upon activation, writing to the internal PROM is enabled. Upon inactivation, reading from the internal PROM is enabled. (8) VDD Positive power supply pin (9) VSS Ground potential pin
Data Sheet U11681EJ2V0DS00
15
PD78P4908
4.3 I/O CIRCUITS FOR PINS AND HANDLING OF UNUSED PINS
Table 4-1 describes the types of I/O circuits for pins and the handling of unused pins. Figure 4-1 shows the configuration of these various types of I/O circuits. Table 4-1. Types of I/O Circuits for Pins and Handling of Unused Pins (1/2)
Pin P00-P07 P10, P11 P12/ASCK2/SCK2 P13/RXD2/SI2 P14/TXD2/SO2 P15-P17 P20/NMI P21/INTP0 P22/INTP1 P23/INTP2/CI P24/INTP3 P25/INTP4/ASCK/SCK1 8-A I/O Input state: To be connected to VDD Output state: To be left open To be connected to VDD 2-A To be connected to VDD 2 Input To be connected to VDD or VSS 8-A 5-A I/O circuit type 5-A I/O I/O Recommended connection method for unused pins Input state: To be connected to VDD Output state: To be left open
P26/INTP5 P27/SI0 P30/RXD/SI1 P31/TXD/SO1 P32/SCK0 P33/SO0 P34/TO0-P37/TO3 P40/AD0-P47/AD7 P50/A8-P57/A15 P60/A16-P63/A19 P64/RD P65/WR P66/WAIT/HLDRQ P67/REFRQ/HLDAK P70/ANI0-P77/ANI7 P90-P97 P100-P104 P105/SCK3 P106/SI3 P107/SO3 ASTB/CLKOUT
2-A
Input
5-A
I/O
Input state: To be connected to VDD Output state: To be left open
10-A
5-A
20 5-A
I/O
To be connected to VDD or VSS Output state : To be left open
Input state:
10-A 8-A 10-A 4 Output To be left open
16
Data Sheet U11681EJ2V0DS00
PD78P4908
Table 4-1. Types of I/O Circuits for Pins and Handling of Unused Pins (2/2)
Pin RESET TEST XT2 XT1 PWM0, PWM1 RX TX AVREF1 AVSS AVDD To be connected to VDD 3 1 3 -- 2 1 -- -- Input Output Input Output -- I/O circuit type I/O Input To be connected to VSS directly To be left open To be connected to VSS To be left open To be connected to VDD or VSS To be left open To be connected to VSS Recommended connection method for unused pins --
Caution When the I/O mode of an I/O dual-function pin is unpredictable, connect the pin to VDD through a resistor of 10 to 100 k (particularly when the voltage of the reset input pin becomes higher than that of the low level input at power-on or when I/O is switched by software). Remark Since type numbers are consistent in the 78K series, those numbers are not always serial in each product. (Some circuits are not included.)
Data Sheet U11681EJ2V0DS00
17
PD78P4908
Figure 4-1. I/O Circuits for Pins
Type 1 Type 2-A VDD Pull-up enable
VDD P
IN N IN Type 2 IN Schmitt trigger input with hysteresis characteristics Type 3 VDD P-ch Data N-ch OUT Output disable Input enable Type 4 VDD Data P OUT Output disable N Pull-up enable Data Push-pull output which can output high impedance (both the positive and negative channels are off.) Type 10-A VDD Pull-up enable VDD P IN/OUT N Output disable P Type 20 Output disable Type 8-A Pull-up enable Data
P
Schmitt trigger input with hysteresis characteristics Type 5-A VDD P VDD P IN/OUT N
VDD P VDD P IN/OUT N
VDD Data P IN/OUT N
Data Open drain Output disable
Comparator Type 12 Analog output voltage P OUT N Input enable + - VREF (Threshold voltage) P N
18
Data Sheet U11681EJ2V0DS00
PD78P4908
5. INTERNAL MEMORY SIZE SELECT REGISTER (IMS)
This register enables the software to avoid using part of the internal memory. The IMS can be set to establish the same memory mapping as used in mask ROM products that have different internal memory (ROM and RAM) configurations. The IMS is set using 8-bit memory operation instructions. A RESET input sets the IMS to FFH. Figure 5-1. Internal Memory Size Select Register (IMS)
7 IMS IMS7 6 IMS6 5 IMS5 4 IMS4 3 IMS3 2 IMS2 1 IMS1 0 IMS0 Address 0FFFCH Reset value FFH R/W W
IMS0-7 FFH EEH
Other than the above
Memory size Same as the PD784908 Same as the PD784907 Not to be set
The IMS is not contained in a mask ROM product (PD784907 or PD784908). But the action is not affected if the write command to the IMS is executed to the mask ROM product.
Data Sheet U11681EJ2V0DS00
19
PD78P4908
6. PROM PROGRAMMING
The PD78P4908 has an on-chip 128-KB PROM device for use as program memory. When programming, set the VPP and RESET pins for PROM programming mode. See 2. PIN CONFIGURATION (TOP VIEW) (2) PROM programming mode with regard to handling of other, unused pins. 6.1 OPERATION MODE
PROM programming mode is selected when +6.5 V is added to the VDD pin, +12.5 V is added to the VPP pin, or low-level input is added to the RESET pin. This mode can be set to operation mode by setting the CE pin, OE pin, and PGM pin as shown in Table 6-1 below. In addition, the PROM contents can be read by setting read mode. Table 6-1. PROM Programming Operation Mode
Pin Operation mode Page data latch Page write Byte write Program verify Program inhibit L +12.5 V +6.5 V H H L L x x Read Output disable Standby +5 V +5 V L L H L H H L H L L H x H L L H H L H x x Data output High impedance High impedance Data input High impedance Data input Data output High impedance RESET VPP VDD CE OE PGM D0-D7
Remark x = L or H
20
Data Sheet U11681EJ2V0DS00
PD78P4908
(1) Read mode Set CE to L and OE to L to set read mode. (2) Output disable mode Set OE to H to set high impedance for data output and output disable mode. Consequently, if several PD78P4908 devices are connected to a data bus, the OE pins can be controlled to select data output from any of the devices. (3) Standby mode Set CE to H to set standby mode. In this mode, data output is set to high impedance regardless of the OE setting. (4) Page data latch mode At the beginning of page write mode, set CE to H, PGM to H, and OE to L to set page data latch mode. In this mode, 1 page (4 bytes) of data are latched to the internal address/data latch circuit. (5) Page write mode After latching the address and data for one page (4 bytes) using page data latch mode, adding a 0.1 ms program pulse (active, low) to the PGM pin with both CE and OE set to H causes page write to be executed. Later, setting both CE and OE to L causes program verification to be executed. If programming is not completed after one program pulse, the write and verify operations may be repeated X times (where X 10). (6) Byte write mode Adding a 0.1 ms program pulse (active, low) to the PGM pin with setting CE to L and OE to H causes byte write to be executed. Later, setting OE to L causes program verification to be executed. If programming is not completed after one program pulse, the write and verify operations may be repeated X times (where X 10). (7) Program verify mode Set CE to L, PGM to H, and OE to L to set program verify mode. Use verify mode for verification following each write operation. (8) Program inhibit mode Program inhibit mode is used to write to a single device when several PD78P4908 devices are connected in parallel to OE , VPP, and D0 to D7 pins. Use the page write mode or byte write mode described above for each write operation. Write operations cannot be done for devices in which the PGM pin has been set to H.
Data Sheet U11681EJ2V0DS00
21
PD78P4908
6.2 PROM WRITE SEQUENCE Figure 6-1. Page Program Mode Flowchart
Start Address = G VDD = +6.5 V, VPP = +12.5 V X=0 Latch Address = Address + 1 Latch Address = Address + 1 Latch Address = Address + 1 Latch X=X+1 0.1 ms program pulse No X = 10 ? Yes
Address = Address + 1
Verify 4 bytes Pass No Address = N ? Yes VDD = 4.0 to 5.5 V, VPP = VDD
Fail
Pass
Verify all bytes All pass Write end
Fail
Defective
Remark G = Start address N = Program end address
22
Data Sheet U11681EJ2V0DS00
PD78P4908
Figure 6-2. Page Program Mode Timing
Page data latch
Page program
Program verify
A2-A16
A0, A1
Hi-Z D0-D7 Data input VPP VPP VDD VDD + 1.5 VDD VDD VIH CE VIL VIH PGM VIL VIH OE VIL
Hi-Z Data output
Data Sheet U11681EJ2V0DS00
23
PD78P4908
Figure 6-3. Byte Program Mode Flowchart
Start Address = G VDD = +6.5 V, VPP = +12.5 V X= 0 X= X + 1 0.1 ms program pulse Fail No X = 10 ? Address = Address + 1 Yes
Verify Pass No Address = N ? Yes VDD = 4.0 to 5.5 V, VPP = VDD Pass
Verify all bytes All pass Write end
Fail
Defective
Remark G = Start address N = Program end address
24
Data Sheet U11681EJ2V0DS00
PD78P4908
Figure 6-4. Byte Program Mode Timing
Program Program verify
A0-A16
D0-D7
Hi-Z
Data input
Hi-Z
Data output
Hi-Z
VPP VPP VDD
VDD + 1.5 VDD VDD
VIH CE VIL VIH PGM VIL VIH OE VIL
Cautions 1. Add VDD before VPP, and turn off the VDD after VPP. 2. Do not allow VPP to exceed 13.5 V including overshoot. 3. Reliability problems may result if the device is inserted or pulled out while 12.5 V is applied at VPP.
Data Sheet U11681EJ2V0DS00
25
PD78P4908
6.3 PROM READ SEQUENCE
Follow this sequence to read the PROM contents to an external data bus (D0 to D7). (1) Set the RESET pin to low level and add 5 V to the VPP pin. See 2. PIN CONFIGURATION (TOP VIEW) (2) PROM programming mode with regard to handling of other, unused pins. (2) Add 5 V to the VDD and VPP pins. (3) Input the data address to be read to pins A0 to A16. (4) Set read mode. (5) Output the data to pins D0 to D7. Figure 6-5 shows the timing of steps (2) to (5) above. Figure 6-5. PROM Read Timing
A0-A16
Address input
CE (input)
OE (input)
D0-D7
Hi-Z
Data output
Hi-Z
7. SCREENING ONE-TIME PROM PRODUCTS
NEC cannot execute a complete test of one-time PROM products (PD78P4908GF-3BA) due to their structure before shipment. It is recommended that you screen (verify) PROM products after writing necessary data into them and storing them at 125C for 24 hours.
26
Data Sheet U11681EJ2V0DS00
PD78P4908
8. ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (TA = 25 C)
Parameter Supply voltage Symbol VDD AVDD AVSS Input voltage VI1 VI2 Analog input voltage Output voltage Output low current VAN VO IOL One pin Total for the P00-P07, P30P37, P54-P57, P60-P67, and P100-P107 pins Total for the P10-P17, P40P47, P50-P53, P70-P77, P90-P97, PWM0, PWM1, and TX pins Output high current IOH One pin Total for the P00-P07, P30P37, P54-P57, P60-P67, and P100-P107 pins Total for the P10-P17, P40P47, P50-P53, P70-P77, P90-P97, PWM0, PWM1, and TX pins A/D converter reference input voltage Operating ambient temperature Storage temperature AVREF1 For pins other than VPP, A9 VPP, A9 Conditions Rating -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to +0.3 -0.3 to VDD + 0.3 -0.3 to +13.5 AVSS - 0.3 to AVREF1 + 0.3 -0.3 to VDD + 0.3 10 50 Unit V V V V V V V mA mA
50
mA
-6 -30
mA mA
-30
mA
-0.3 to VDD + 0.3
V C C
TA Tstg
-40 to +85 -65 to +150
Caution Absolute maximum ratings are rated values beyond which physical damage will be caused to the product; if the rated value of any of the parameters in the above table is exceeded, even momentarily, the quality of the product may deteriorate. Always use the product within its rated values. Remark Unless otherwise stated, the characteristics of a dual-function pin are the same as those of a port pin.
Data Sheet U11681EJ2V0DS00
27
PD78P4908
OPERATING CONDITIONS * Operating ambient temperature (TA): -40 C to +85 C * Power supply voltage and clock cycle time: See Figure 8-1. * Internal regulator operation selected (REGOFF pin: low level) Figure 8-1. Power Supply Voltage and Clock Cycle Time
10,000 4,000 Clock cycle time tCYK [ns]
1,000 Guaranteed operating range 159 100 79
10
0
1
2 3 4 5 Power supply voltage [V]
6
7
CAPACITANCE (TA = 25 C, VDD = VSS = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO Conditions f = 1 MHz 0 V on pins other than measured pins MIN. TYP. MAX. 15 15 15 Unit pF pF pF
28
Data Sheet U11681EJ2V0DS00
PD78P4908
MAIN OSCILLATOR CHARACTERISTICS (TA = -40 C to +85 C, VDD = 4.0 to 5.5 V, VSS = 0 V)
Parameter Oscillator frequency fXX Symbol Conditions Ceramic or crystal resonator MIN. 2 MAX. 12.58 Unit MHz
Caution When using the clock generator, run wires according to the following rules to avoid effects such as stray capacitance: * Minimize the wiring length. * Never cause the wires to cross other signal lines. * Never cause the wires to run near a line carrying a large varying current. * The grounding point of the capacitor of the oscillator circuit must always be the same potential as VSS1. Never connect the capacitor to a ground pattern carrying a large current. * Never extract a signal from the oscillator. Remark Connect a 12.582912 or 6.291456 MHz oscillator to operate the internal clock timer with the main clock. CLOCK OSCILLATOR CHARACTERISTICS (TA = -40 C to +85 C, VDD = 4.0 to 5.5 V, VSS = 0 V)
Parameter Oscillator frequency Oscillation settling time Symbol fXT tSXT Conditions Ceramic or crystal resonator VDD = 4.5 to 5.5 V MIN. 32 TYP. 32.768 1.2 MAX. 35 2 10 Oscillation hold voltage Watch timer operating voltage VDDXT VDDW 4.0 4.0 5.5 5.5 Unit kHz s s V V
Data Sheet U11681EJ2V0DS00
29
PD78P4908
DC CHARACTERISTICS (TA = -40 C to +85 C, VDD = AVDD = 4.0 to 5.5 V, VSS = AVSS = 0 V) (1/2)
Parameter Input low voltageNote 5 Symbol VIL1 Conditions For pins other than those described in Notes 1 and 2 For pins described in Note 1 VDD = 4.5 to 5.5 V For pins described in Note 2 For pins other than those described in Notes 1 and 2 For pins described in Note 1 VDD = 4.5 to 5.5 V For pins described in Note 2 IOL = 20 A IOL = 100 A IOL = 2 mA VOL2 IOL = 8 mA For pins described in Note 4 VDD = 4.5 to 5.5 V IOH = -20 A IOH = -100 A IOH = -2 mA VOH2 VDD = 4.5 to 5.5 V IOH = -5 mA For pins described in Note 3 VDD - 0.1 VDD - 0.2 VDD - 1.0 VDD - 2.4 MIN. -0.3 TYP. MAX. 0.3 VDD Unit V
VIL2 VIL3
-0.3 -0.3
0.2 VDD +0.8
V V
Input high voltage
VIH1
0.7 VDD
VDD + 0.3
V
VIH2 VIH3
0.8 VDD 2.2
VDD + 0.3 VDD + 0.3
V V
Output low voltage
VOL1
0.1 0.2 0.4 1.0
V V V V
Output high voltage
VOH1
V V V V
Notes 1. X1, X2, RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0, P33/SO0, P105/SCK3, P106/SI3, P107/SO3, XT1, XT2 2. P40/AD0-P47/AD7, P50/A8-P57/A15, P60/A16-P67/REFRQ/HLDAK, P00-P07 3. P00-P07 4. P10-P17, P40/AD0-P47/AD7, P50/A8-P57/A15 5. Other than pull-up resistors
30
Data Sheet U11681EJ2V0DS00
PD78P4908
DC CHARACTERISTICS (TA = -40 C to +85 C, VDD = AVDD = 4.0 to 5.5 V, VSS = AVSS = 0 V) (2/2)
Parameter Input leakage current Symbol ILI1 0 V VI VDD Conditions For pins other than X1 and XT1 X1, XT1 0 V VO VDD Operation mode fXX = 12.58 MHz VDD = 4.5 to 5.5 V fXX = 6.29 MHz VDD = 4.0 to 5.5 V fXX = 12.58 MHz VDD = 4.5 to 5.5 V fCLK = fXX/8 (STBC = B1H) Peripheral operation stops. fXX = 6.29 MHz VDD = 4.0 to 5.5 V fCLK = fXX/8 (STBC = 31H) Peripheral operation stops. IDD3 IDLE mode fXX = 12.58 MHz VDD = 4.5 to 5.5 V fXX = 6.29 MHz VDD = 4.0 to 5.5 V 15 20 10 MIN. TYP. MAX. 10 20 10 40 20 Unit
A A A
mA mA
ILI2 Output leakage current VDD supply current Note ILO IDD1
IDD2
HALT mode
5.2
10.4
mA
2.6
5.2
mA
2.4 1.8
4.8 3.6
mA mA
Pull-up resistor
RL
VI = 0 V
80
k
Note These values are valid when the internal regulator is ON (REGOFF pin = low level). They do not include the AVDD and AVREF1 currents.
Data Sheet U11681EJ2V0DS00
31
PD78P4908
AC CHARACTERISTICS (TA = -40C to +85C, VDD = AVDD = 4.0 to 5.5 V, AVSS = VSS = 0 V) (1) Read/write operation
Parameter Address setup time (to ASTB) ASTB high-level width Address hold time (to ASTB) Address hold time (to RD) Delay from address to RD Address float time (to RD) Delay from address to data input Symbol tSAST VDD = 5.0 V Conditions (0.5 + a)T - 11 MAX. Unit ns
MIN. 29
tWSTH tHSTLA tHRA tDAR tFRA tDAID
VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V
(0.5 + a)T - 17 0.5T - 19 0.5T - 14 (1 + a)T - 5
23 21 26 74 0
ns ns ns ns ns 400 ns
VDD = 5.0 V
(2.5 + a + n)T - 37
Delay from ASTB to data input tDSTID Delay from RD to data input Delay from ASTB to RD Data hold time (to RD) Delay from RD to address active Delay from RD to ASTB RD low-level width Delay from address to WR Address hold time (to WR) Delay from ASTB to data output tDRID tDSTR tHRID tDRA
VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V
(2 + n)T - 35 (1.5 + n)T - 40 0.5T - 9 31 0
283 238
ns ns ns ns ns
VDD = 5.0 V
0.5T - 2
38
tDRST tWRL tDAW tHWA tDSTOD
VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V
0.5T - 9 (1.5 + n)T - 25 (1 + a)T - 5 0.5T - 14 0.5T + 15
31 94 74 26 55
ns ns ns ns ns
Delay from WR to data output tDWOD Delay from ASTB to WR Data setup time (to WR) Data hold time (to WR) Delay from WR to ASTB WR low-level width tDSTW tSODWR tHWOD tDWST tWWL VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V 0.5T - 9 (1.5 + n)T - 20 0.5T - 14 0.5T - 9 (1.5 + n)T - 25 31 99 26 31 94
15
ns ns ns ns ns ns
Remark T: a: n:
tCYK (system clock cycle time) VDD = 5.0 V T = 79 ns (MIN.) 1 during address wait, otherwise, 0 Number of wait states (n 0)
32
Data Sheet U11681EJ2V0DS00
PD78P4908
(2) External wait timing
Parameter Symbol VDD = 5.0 V Conditions (2 + a)T - 40 MIN. MAX. 198 Unit ns
Delay from address to WAIT tDAWT input Delay from ASTB to WAIT input tDSTWT
VDD = 5.0 V
1.5T - 40
79
ns
Hold time from ASTB to WAIT tHSTWT Delay from ASTB to WAIT Delay from RD to WAIT input Hold time from RD to WAIT Delay from RD to WAIT Delay from WAIT to data input Delay from WAIT to RD Delay from WAIT to WR Delay from WR to WAIT input Hold time from WR to WAIT Delay from WR to WAIT tDSTWTH tDRWTL
VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V
(0.5 + n)T + 5 (1.5 + n)T - 40 T - 40
124 238 39
ns ns ns
tHRWT tDRWTH tDWTID
VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V
nT + 5 (1 + n)T - 40 0.5T - 5
84 198 35
ns ns ns
tDWTR tDWTW tDWWTL
VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V
0.5T 0.5T T - 40
40 40 39
ns ns ns
tHWWT tDWWTH
VDD = 5.0 V VDD = 5.0 V
nT + 5 (1 + n)T - 40
84 198
ns ns
Remark T: a: n:
tCYK (system clock cycle time) VDD = 5.0 V T = 79 ns (MIN.) 1 during address wait, otherwise, 0 Number of wait states (n 0)
Data Sheet U11681EJ2V0DS00
33
PD78P4908
(3) Bus hold timing
Parameter Delay from HLDRQ to float Symbol tFHQC VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V Conditions (2 + 4 + a + n)T + 50 (3 + 4 + a + n)T + 30 T + 30 2T + 40 T - 20 59 MIN. MAX. 765 825 109 199 Unit ns ns ns ns ns
Delay from HLDRQ to HLDAK tDHQHHAH Delay from float to HLDAK tDCFHA
Delay from HLDRQ to HLDAK tDHQLHAL Delay from HLDRQ to active tDHAC
Remark T: a: n:
tCYK (system clock cycle time) VDD = 5.0 V T = 79 ns (MIN.) 1 during address wait, otherwise, 0 Number of wait states (n 0)
(4) Refresh timing
Parameter Random read/write cycle time REFRQ low-level pulse width Delay from ASTB to REFRQ Delay from RD to REFRQ Delay from WR to REFRQ Delay from REFRQ to ASTB REFRQ high-level pulse width Symbol tRC tWRFQL tDSTRFQ tDRRFQ tDWRFQ tDRFQST tWRFQH VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V Conditions 3T 1.5T - 25 0.5T - 9 1.5T - 9 1.5T - 9 0.5T - 9 1.5T - 25 MIN. 238 94 31 110 110 31 94 MAX. Unit ns ns ns ns ns ns ns
Remark T: tCYK (system clock cycle time) VDD = 5.0 V T = 79 ns (MIN.)
34
Data Sheet U11681EJ2V0DS00
PD78P4908
SERIAL OPERATION (TA = -40 C to +85 C, VDD = 4.0 to 5.5 V, AVSS = VSS = 0 V) (1) CSI, CSI3
Parameter Serial clock cycle time (SCK0, SCK3) Symbol tCYSK0 Input Conditions fCLK = fXX Other than fCLK = fXX Output Other than fCLK = fXX/8 fCLK = fXX/8 Serial clock low-level width (SCK0, SCK3) tWSKL0 Input fCLK = fXX Other than fCLK = fXX Output Other than fCLK = fXX/8 fCLK = fXX/8 Serial clock high-level width (SCK0, SCK3) tWSKH0 Input fCLK = fXX Other than fCLK = fXX Output Other than fCLK = fXX/8 fCLK = fXX/8 Setup time for SI0, SI3 (to SCK0, SCK3) Hold time for SI0, SI3 (to SCK0, SCK3) Output delay time for SO0, SO3 (to SCK0, SCK3) tSSSK0 MIN. 8/fXX 4/fCLK 8/fXX 16/fXX 4/fXX - 40 2/fCLK - 40 4/fXX - 40 8/fXX - 40 4/fXX - 40 2/fCLK - 40 4/fXX - 40 8/fXX - 40 80 ns ns MAX. Unit ns ns ns ns ns
s
s
tHSSK0
External clock Internal clock
1/fCLK + 80 80 External clock Internal clock 0 0 0 0 0.5tCYSK0 - 40 1/fCLK + 150 150 1/fCLK + 400 400
ns
tDSBSK1
CMOS push-pull output
ns ns ns ns ns
tDSBSK2
Open-drain output RL = 1 k
External clock Internal clock
Output hold time for SO0, SO3 (to SCK0, SCK3)
tHSBSK
When data is transferred
Remarks 1. The values in this table are those when fXX = 12.58 MHz, CL is 100 pF. 2. fCLK: 3. fXX : System clock frequency (selectable from fXX, fXX/2, fXX/4, and fXX/8 by the standby control register (STBC)) Oscillation frequency (fXX = 12.58 MHz or fXX = 6.29 MHz)
Data Sheet U11681EJ2V0DS00
35
PD78P4908
(2) IOE1, IOE2 (TA = -40 C to +85 C, VDD = AVDD = 4.0 to 5.5 V, AVSS = VSS = 0 V)
Parameter Serial clock cycle time (SCK1, SCK2) Symbol tCYSK1 Input Conditions VDD = 4.5 to 5.5 V MIN. 640 1,280 Output Serial clock low-level width (SCK1, SCK2) tWSKL1 Input Internal, divided by 8 VDD = 4.5 to 5.5 V T 280 600 Output Serial clock high-level width (SCK1, SCK2) tWSKH1 Input Internal, divided by 8 VDD = 4.5 to 5.5 V 0.5T - 40 280 600 Output Setup time for SI1 and SI2 (to SCK1, SCK2) Hold time for SI1 and SI2 (to SCK1, SCK2) tSSSK1 Internal, divided by 8 0.5T - 40 40 MAX. Unit ns ns ns ns ns ns ns ns ns ns
tHSSK1
40
ns
Output delay time for SO1 and tDSOSK SO2 (to SCK1, SCK2) Output hold time for SO1 and SO2 (to SCK1, SCK2) tHSOSK When data is transferred
0
50
ns
0.5tCYSK1 - 40
ns
Remarks 1. The values in this table are those when CL is 100 pF. 2. T: Serial clock cycle set by software. The minimum value is 8/fXX. (3) UART, UART2 (TA = -40 C to +85 C, VDD = AVDD = 4.0 to 5.5 V, AVSS = VSS = 0 V)
Parameter ASCK clock input cycle time Symbol tCYASK Conditions VDD = 4.5 to 5.5 V MIN. 160 320 ASCK clock low-level width tWASKL VDD = 4.5 to 5.5 V 65 120 ASCK clock high-level width tWASKH VDD = 4.5 to 5.5 V 65 120 MAX. Unit ns ns ns ns ns ns
36
Data Sheet U11681EJ2V0DS00
PD78P4908
CLOCK OUTPUT OPERATION (TA = -40C to +85C, VDD = AVDD = 4.0 to 5.5 V, AVSS = VSS = 0 V)
Parameter CLKOUT cycle time CLKOUT low-level width Symbol tCYCL tCLL nT VDD = 4.5 to 5.5 V, 0.5T - 10 0.5T - 20 CLKOUT high-level width tCLH VDD = 4.5 to 5.5 V, 0.5T - 10 0.5T - 20 CLKOUT rise time tCLR 4.5 V VDD < 5.5 V 4.0 V VDD < 4.5 V CLKOUT fall time tCLF 4.5 V VDD < 5.5 V 4.0 V VDD < 4.5 V Conditions MIN. 79 30 20 30 20 10 20 10 20 MAX. 32,000 Unit ns ns ns ns ns ns ns ns ns
Remark n: T:
Dividing ratio set by software in the CPU (n = 1, 2, 4, 8, and 16) tCYK (system clock cycle time)
OTHER OPERATIONS (TA = -40 C to +85 C, VDD = AVDD = 4.0 to 5.5 V, AVSS = VSS = 0 V)
Parameter NMI low-level width NMI high-level width INTP0 low-level width INTP0 high-level width Low-level width for INTP1INTP3 and CI High-level width for INTP1INTP3 and CI Symbol tWNIL tWNIH tWIT0L tWIT0H tWIT1L Conditions MIN. 10 10 4 tCYSMP 4 tCYSMP 4 tCYCPU MAX. Unit
s s
ns ns ns
tWIT1H
4 tCYCPU
ns
Low-level width for INTP4 and tWIT2L INTP5 High-level width for INTP4 and tWIT2H INTP5 RESET low-level widthNote RESET high-level width tWRSL tWRSH
10
s s s s
10
10 10
Note Use the RESET low-level width to ensure the lapse of the oscillation settling time when the power is applied. Remark tCYSMP: Sampling clock set by software tCYCPU: CPU operation clock set by software in the CPU
Data Sheet U11681EJ2V0DS00
37
PD78P4908
A/D CONVERTER CHARACTERISTICS (TA = -40 C to +85 C, VDD = AVDD = AVREF1 = 4.0 to 5.5 V, AVSS = VSS = 0 V)
Parameter Resolution Total errorNote IEAD = 00H FR = 0 FR = 1 IEAD = 01H Quantization error Conversion time tCONV FR = 1 120/fCLK FR = 0 240/fCLK Sampling time tSAMP FR = 1 18/fCLK FR = 0 36/fCLK Analog input impedance AVREF1 impedance AVDD power supply voltage RAN RREF1 AIDD1 AIDD2 CS = 1 CS = 0, STOP mode 3 9.5 19.1 1.4 2.9 1,000 10 2.0 1.0 5.0 20 VDD = 4.5 to 5.5 V 1 Symbol Conditions MIN. 8 0.6 1.5 2.2 1/2 480 960 72 144 TYP. MAX. Unit bit % % % LSB
s s s s
M k mA
A
Note Quantization error is not included. This parameter is indicated as the ratio to the full-scale value. Caution To execute the conversion by the A/D converter set port 7, multiplexed with the A/D input lines, to output mode to prevent data from being inverted. Remark fCLK: System clock frequency (selectable from fXX, fXX/2, fXX/4, and fXX/8 by the standby control register (STBC)) IEBus CONTROLLER CHARACTERISTICS (TA = -40C to +85C, VDD = AVDD = AVREF1 = 4.5 to 5.5 V, AVSS = VSS = 0 V)
Parameter IEBus standard frequencyNote 1 Driver delay time (delay from TX output to bus line)Note 2 Receiver delay time (delay from bus line to RX output)Note 2 Transmission delay on busNote 2 Symbol fS Conditions Transfer speed: mode 1 MIN. 6.20 TYP. 6.29 MAX. 6.39 Unit MHz
tDTX
CL = 50 pFNote 3
1.5
s s
tDRX
0.7
tDBUS
0.85
s
Notes 1. The value conforms to the IEBus standard. The IEBus controller is operable within the range of the oscillator frequency of oscillator characteristics. 2. The value is measured when IEBus system clock: fX = 6.29 MHz. 3. CL is the load capacitance of TX output line.
38
Data Sheet U11681EJ2V0DS00
PD78P4908
DATA RETENTION CHARACTERISTICS (TA = -40 C to +85 C)
Parameter Data retention voltage Data retention current Symbol VDDDR IDDDR STOP mode STOP mode VDDDR = 2.5 V, AVREF = 0 V Note 1 VDDDR = 4.0 to 5.5 V, AVREF1 = 0 V Note 1 VDD rise time VDD fall time VDD hold time (to STOP mode setting) STOP clear signal input time Oscillation settling time tRVD tFVD tHVD 200 200 0 Conditions MIN. 2.5 2 TYP. MAX. 5.5 10 Unit V
A A s s
ms
10
50
tDREL tWAIT Crystal resonator Ceramic resonator
0 30 5 0 0.9 VDDDR 0.1 VDDDR VDDDR
ms ms ms V V
Input low voltage Input high voltage
VIL VIH
Specific
pins Note 2
Notes 1. Valid when input voltages to the pins described in Note 2 satisfy VIL or VIH in the above table. 2. RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0, P33/SO0, P105/SCK3, P106/SI3, and P107/SO3 pins AC TIMING TEST POINTS
VDD - 1 V
0.8 VDD or 2.2 V Test points 0.8 V
0.8 VDD or 2.2 V 0.8 V
0.45 V
Data Sheet U11681EJ2V0DS00
39
PD78P4908
TIMING WAVEFORM (1) Read operation
tWSTH ASTB tSAST tHSTLA A8-A19 tDSTID tDRST
tDAID AD0-AD7 tDSTR tDAR RD tWRL tFRA tDRID
tHRA
tHRID tDRA
(2) Write operation
tWSTH ASTB tSAST tHSTLA A8-A19 tDSTOD tDWST
tHWA AD0-AD7 tDSTW tDAW WR tWWL tDWOD tSODWR tHWOD
40
Data Sheet U11681EJ2V0DS00
PD78P4908
HOLD TIMING
ASTB, A8-A19, AD0-AD7, RD, WR tFHQC HLDRQ tDHQHHAH HLDAK tDHQLHAL tDCFHA tDHAC
EXTERNAL WAIT SIGNAL INPUT TIMING (1) Read operation
ASTB tDSTWTH tHSTWTH
tDSTWT A8-A19
AD0-AD7 tDAWT RD tDRWTL WAIT tHRWT tDRWTH tDWTR tDWTID
(2) Write operation
ASTB tDSTWTH tHSTWTH
tDSTWT A8-A19
AD0-AD7 tDAWT WR tDWWTL WAIT tHWWT tDWWTH tDWTW
Data Sheet U11681EJ2V0DS00
41
PD78P4908
REFRESH TIMING WAVEFORM (1) Random read/write cycle
tRC ASTB
WR tRC RD tRC tRC tRC
(2) When refresh memory is accessed for a read and write at the same time
ASTB
RD, WR tDSTRFQ tDRFQST tWRFQH
REFRQ tWRFQL
(3) Refresh after a read
ASTB tDRFQST RD tDRRFQ REFRQ tWRFQL
(4) Refresh after a write
ASTB tDRFQST WR tDWRFQ REFRQ tWRFQL
42
Data Sheet U11681EJ2V0DS00
PD78P4908
SERIAL OPERATION (CSI, CSI3)
tWSKL0 SCK0, SCK3 tCYSK0 SI0, SI3
tWSKH0
tSSSK0 tHSSK0 Input data tDSBSK1 tHSBSK1
SO0, SO3
Output data
SERIAL OPERATION (IOE1, IOE2)
tWSKL1 SCK1, SCK2 tCYSK1 SI1, SI2 tDSOSK SO1, SO2 tHSOSK tSSSK1 tHSSK1 tWSKH1
Input data
Output data
SERIAL OPERATION (UART, UART2)
tWASKH tWASKL
ASCK, ASCK2 tCYASK
CLOCK OUTPUT TIMING
tCLH tCLL
CLKOUT tCLR tCYCL tCLF
Data Sheet U11681EJ2V0DS00
43
PD78P4908
INTERRUPT REQUEST INPUT TIMING
tWNIH tWNIL
NMI
tWIT0H
tWIT0L
INTP0
tWIT1H
tWIT1L
CI, INTP1-INTP3
tWIT2H
tWIT2L
INTP4, INTP5
RESET INPUT TIMING
tWRSH tWRSL
RESET
44
Data Sheet U11681EJ2V0DS00
PD78P4908
EXTERNAL CLOCK TIMING
tWXH tWXL
X1 tXR tCYX tXF
DATA RETENTION CHARACTERISTICS
STOP mode setting
VDD tHVD tFVD
VDDDR tRVD tDREL tWAIT
RESET
NMI (Clearing by falling edge)
NMI (Clearing by rising edge)
Data Sheet U11681EJ2V0DS00
45
PD78P4908
DC PROGRAMMING CHARACTERISTICS (TA = 25C 5C, VSS = 0 V)
Parameter High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage Output leakage current VDDP supply voltage
Symbol VIH
SymbolNote 1 VIH
Conditions
MIN. 2.2
TYP.
MAX. VDDP + 0.3
Unit V V
VIL
VIL 0 VI VDDP Note 2 IOH = -400 A IOL = 2.1 mA 0 VO VDDP, OE = VIH Program memory write mode Program memory read mode
-0.3
+0.8 10
ILIP VOH
ILI VOH
A
V
2.4
VOL
VOL
0.45 10
V
ILO
-
A
VDDP
VCC
6.25 4.5 12.2
6.5 5.0 12.5 VPP = VDDP 10 10 5 1.0
6.75 5.5 12.8
V V V V
VPP supply voltage
VPP
VPP
Program memory write mode Program memory read mode
VDDP supply current
IDD
IDD
Program memory write mode Program memory read mode
40 40 50 100
mA mA mA
VPP supply current
IPP
IPP
Program memory write mode Program memory read mode
A
Notes 1. Symbols for the corresponding PD27C1001A 2. The VDDP represents the VDD pin as viewed in the programming mode.
46
Data Sheet U11681EJ2V0DS00
PD78P4908
AC PROGRAMMING CHARACTERISTICS (TA = 25C 5C, VSS = 0 V) PROM Write Mode (Page Program Mode)
Parameter Address setup time CE set time Input data setup time Address hold time SymbolNote 1 tAS tCES tDS tAH tAHL tAHV Input data hold time Output data hold time VPP setup time VDDP setup time Initial program pulse width OE set time Valid data delay time from OE OE pulse width in the data latch PGM setup time CE hold time OE hold time tDH tDF tVPS tVDSNote 2 tPW tOES tOE tLW tPGMS tCEH tOEH 1 2 2 2 Conditions MIN. 2 2 2 2 2 0 2 0 2 2 0.095 2 1 2 0.1 0.105 130 TYP. MAX. Unit
s s s s s s s
ns
s s
ms
s
ns
s s s s
Notes 1. These symbols (except tVDS) correspond to those of the corresponding PD27C1001A. 2. For PD27C1001A, read tVDS as tVCS.
Data Sheet U11681EJ2V0DS00
47
PD78P4908
PROM Write Mode (Byte Program Mode)
Parameter Address setup time CE set time Input data setup time Address hold time Input data hold time Output data hold time VPP setup time VDDP setup time Initial program pulse width OE set time Valid data delay time from OE Symbol Note 1 tAS tCES tDS tAH tDH tDF tVPS tVDSNote 2 tPW tOES tOE Conditions MIN. 2 2 2 2 2 0 2 2 0.095 2 1 2 0.1 0.105 130 TYP. MAX. Unit
s s s s s
ns
s s
ms
s
ns
Notes 1. These symbols (except tVDS) correspond to those of the corresponding PD27C1001A. 2. For PD27C1001A, read tVDS as tVCS. PROM Read Mode
Parameter Data output time from address Delay from CE to data output Delay from OE to data output Data hold time to OE or CE Note 2 Data hold time to address Symbol Note 1 tACC tCE tOE tDF tOH Conditions CE = OE = VIL OE = VIL CE = VIL CE = VIL or OE = VIL CE = OE = VIL 0 0 1 1 MIN. TYP. MAX. 200 2 2 60 Unit ns
s s
ns ns
Notes 1. These symbols correspond to those of the corresponding PD27C1001A. 2. tDF is the time measured from when either OE or CE reaches VIH, whichever is faster.
48
Data Sheet U11681EJ2V0DS00
PD78P4908
PROM Write Mode Timing (Page Program Mode)
Page data latch Page program Program verify
A2-A16 tAS A0, A1 tDS D0-D7 Hi-Z tVPS VPP VPP VDDP tVDS VDDP + 1.5 VDDP VDDP tCES VIH CE VIL VIH PGM VIL VIH OE VIL tLW tOES tPW tCEH tOEH Data input tDH Hi-Z tPGMS tOE Data output tDF Hi-Z tAHL tAHV
tAH
Data Sheet U11681EJ2V0DS00
49
PD78P4908
PROM Write Mode Timing (Byte Program Mode)
Program Program verify
A0-A16 tAS D0-D7 Hi-Z tDS Data input tDH Hi-Z Data output tAH tDF Hi-Z
tDS VPP VPP VDDP
tVPS VDDP + 1.5 VDDP VDDP tVDS VIH CE VIL tCES VIH PGM VIL VIH OE VIL tOES tOE tPW
Cautions 1. VDDP must be applied before VPP, and must be cut after VPP. 2. VPP including overshoot must not exceed 13.5 V. 3. Plugging in or out the board with the VPP pin supplied with 12.5 V may adversely affect its reliability. PROM Read Mode Timing
A0-A16
Valid address
CE tCE OE tDFNote 2 tACCNote 1 D0-D7 Hi-Z tOENote 1 Data output tOH Hi-Z
Notes 1. For reading within tACC, the delay of the OE input from falling edge of CE must be within tACC-tOE. 2. tDF is the time measured from when either OE or CE reaches VIH, whichever is faster.
50
Data Sheet U11681EJ2V0DS00
PD78P4908
9. PACKAGE DRAWING
100PIN PLASTIC QFP (14x20)
A B
80 81
51 50
detail of lead end CD
S Q R
100 1
31 30
F G H I
M
J
P
K M N L
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 23.60.4 20.00.2 14.00.2 17.60.4 0.8 0.6 0.300.10 0.15 0.65 (T.P.) 1.80.2 0.80.2 0.15 +0.10 -0.05 0.10 2.70.1 0.10.1 55 3.0 MAX. INCHES 0.9290.016 0.795 +0.009 -0.008 0.551 +0.009 -0.008 0.6930.016 0.031 0.024 0.012 +0.004 -0.005 0.006 0.026 (T.P.) 0.071 +0.008 -0.009 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 +0.005 -0.004 0.0040.004 55 0.119 MAX. P100GF-65-3BA1-3
NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
Remark The shape and material of the ES version are the same as those of the corresponding mass-produced product.
Data Sheet U11681EJ2V0DS00
51
PD78P4908
10. RECOMMENDED SOLDERING CONDITIONS
The conditions listed below shall be met when soldering the PD78P4908. For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under different conditions. Table 10-1. Soldering Conditions for Surface-Mount Devices
PD78P4908GF-3BA: 100-pin plastic QFP (14 x 20 mm)
Soldering process Infrared ray reflow Soldering conditions Peak package's surface temperature: 235C Reflow time: 30 seconds or less (210C or more) Maximum allowable number of reflow processes: 2 Exposure limit: 7 days Note (20 hours of pre-baking is required at 125C afterward) Peak package's surface temperature: 215C Reflow time: 40 seconds or less (200C or more) Maximum allowable number of reflow processes: 2 Exposure limit: 7 days Note (20 hours of pre-baking is required at 125C afterward) Solder temperature: 260C or less Flow time: 10 seconds or less Number of flow processes: 1 Preheating temperature: 120C MAX. (measured on the package surface) Exposure limit: 7 days Note (20 hours of pre-baking is required at 125C afterward) Partial heating method Terminal temperature: 300C or less Heat time: 3 seconds or less (for one side of a device) - Symbol IR35-207-2
VPS
VP15-207-2
Wave soldering
WS60-207-1
Note Maximum number of days during which the product can be stored at a temperature of 25C and a relative humidity of 65% or less after dry-pack package is opened. Caution Do not apply two or more different soldering methods to one chip (except for partial heating method for terminal sections).
52
Data Sheet U11681EJ2V0DS00
PD78P4908
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for system development using the PD78P4908. See also (5) Notes on using development tools. (1) Language processing software
RA78K4 CC78K4 DF784908 CC78K4-L Assembler package for all 78K/IV series models C compiler package for all 78K/IV series models Device file for PD784908 subseries models C compiler library source file for all 78K/IV series models
(2) PROM write tools
PG-1500 PA-78P4908GF PG-1500 controller PROM programmer Programmer adapter, connects to PG-1500 Control program for PG-1500
(3) Debugging tools * When using the in-circuit emulator IE-78K4-NS
IE-78K4-NS IE-70000-MC-PS-B IE-70000-98-IF-C IE-70000-CD-IF-A In-circuit emulator for all 78K/IV series models Power supply unit for IE-78K4-NS Interface adapter when the PC-9800 series computer (other than a notebook) is used as the host machine (C bus compatible) PC card and interface cable when a notebook is used as the host machine (PCMCIA socket compatible) IE-70000-PC-IF-C Interface adapter when the IBM PC/ATTM compatible is used as the host machine (ISA compatible) Adapter when a computer with a PCI bus as the host machine Emulation board for evaluating PD784908 subseries models Emulation probe for 100-pin plastic QFP (GF-3BA type) Socket for mounting on target system board made for 100-pin plastic QFP (GF-3BA type). Used in LCC mode. Integrated debugger for IE-78K4-NS System simulator for all 78K/IV series models Device file for PD784908 subseries models
IE-7000-PCI-IF IE-784908-NS-EM1Note NP-100GFNote EV-9200GF-100
ID78K4-NS SM78K4 DF784908
Note Under development
Data Sheet U11681EJ2V0DS00
53
PD78P4908
* When using the in-circuit emulator IE-784000-R
IE-784000-R IE-70000-98-IF-C In-circuit emulator for all 78K/IV series models Interface adapter when the PC-9800 series computer (other than a notebook) is used as the host machine (C bus compatible) Interface adapter when the IBM PC/AT compatible is used as the host machine (ISA bus compatible) Adapter when a computer with a PCI bus as the host machine Interface adapter and cable when the EWS is used as the host machine Emulation board for evaluating PD784908 subseries models Emulation board for all 78K/IV series models Conversion board for emulation probes required to use the IE-784908-NSEM1 on the IE-784000-R. The board is not needed when the conventional product IE-784908-R-EM1 is used. Emulation probe for 100-pin plastic QFP (GF-3BA type) Socket for mounting on target system board made for 100-pin plastic QFP (GF-3BA type) Integrated debugger for IE-784000-R System simulator for all 78K/IV series models Device file for PD784908 subseries models
IE-70000-PC-IF-C
IE-7000-PCI-IF IE-78000-R-SV3 IE-784908-NS-EM1 IE-784908-R-EM1 IE-784000-R-EM IE-78K4-R-EX2
EP-78064-GF-R EV-9200GF-100
ID78K4 SM78K4 DF784908
(4) Real-time OS
RX78K/IV MX78K4 Real-time OS for 78K/IV series models OS for 78K/IV series models
54
Data Sheet U11681EJ2V0DS00
PD78P4908
(5) Notes when using development tools * The ID78K4-NS, ID78K4, and SM78K4 can be used in combination with the DF784908. * The CC78K4 and RX78K/IV can be used in combination with the RA78K4 and DF784908. * The NP-100GF is a product from Naito Densei Machida Mfg. Co., Ltd. (044-822-3813). Consult the NEC sales representative for purchasing. * The host machines and operating systems corresponding to each software are shown below.
Host machine [OS] PC PC-9800 series [WindowsTM] IBM PC/AT compatibles [Windows] EWS HP9000 series 700TM [HP-UXTM] SPARCstationTM [SunOSTM, Solaris TM] NEWSTM (RISC) [NEWS-OSTM]
Software RA78K4 CC78K4 PG-1500 controller ID78K4-NS ID78K4 SM78K4 RX78K/IV MX78K4
Note Note Note Note Note
- -
-
Note Software under MS-DOS
Data Sheet U11681EJ2V0DS00
55
PD78P4908
APPENDIX B CONVERSION SOCKET (EV-9200GF-100) PACKAGE DRAWING
Connect the PD78P4908GF-3BA (100-pin plastic QFP (14 x 20 mm)) to the circuit board in combination with the EV-9200GF-100. Figure B-1. Package Drawings of EV-9200GF-100 (Reference)
E
A B F
M N
O
R D C S
K
EV-9200GF-100
1
No.1 pin index
P
G H I EV-9200GF-100-G0 ITEM A B C D E F G H I J K L M N O P Q R S MILLIMETERS 24.6 21 15 18.6 4-C 2 0.8 12.0 22.6 25.3 6.0 16.6 19.3 8.2 8.0 2.5 2.0 0.35 INCHES 0.969 0.827 0.591 0.732 4-C 0.079 0.031 0.472 0.89 0.996 0.236 0.654 076 0.323 0.315 0.098 0.079 0.014
2.3 1.5
0.091 0.059
56
Data Sheet U11681EJ2V0DS00
Q
L
J
PD78P4908
Figure B-2. Recommended Pattern to Mount EV-9200GF-100 on a Substrate (Reference)
G
J K
D
L
C B A EV-9200GF-100-P1E ITEM A B C D E F G H I J K L Caution MILLIMETERS 26.3 21.6 INCHES 1.035 0.85
0.650.02 x 29=18.850.05 0.026 +0.001 x 1.142=0.742+0.002 -0.002 -0.002 0.650.02 x 19=12.350.05 0.026 +0.001 x 0.748=0.486 +0.003 -0.002 -0.002 15.6 20.3 12 0.05 6 0.05 0.35 0.02 0.614 0.799 0.472 +0.003 -0.002 0.236 +0.003 -0.002 0.014 +0.001 -0.001
2.36 0.03 2.3 1.57 0.03
0.093+0.001 -0.002 0.091 0.062+0.001 -0.002
Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E).
I
H
F E
Data Sheet U11681EJ2V0DS00
57
PD78P4908
APPENDIX C RELATED DOCUMENTS
Documents Related to Devices
Document name Document No. Japanese English U11680E This document U11787E -- U10905E -- -- U10095E
PD784907, 784908 Data Sheet PD78P4908 Data Sheet PD784908 Subseries User's Manual - Hardware PD784908 Subseries Special Function Registers
78K/IV Series User's Manual - Instruction 78K/IV Series Instruction Table 78K/IV Series Instruction Set 78K/IV Series Application Note Software Basic
U11680J U11681J U11787J U11589J U10905J U10594J U10595J U10095J
Documents Related to Development Tools (User's Manual)
Document name RA78K4 Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor CC78K4 C Compiler Operation Language PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOSTM) Base PG-1500 Controller IBM PC Series (PC DOS TM) Base IE-78K4-NS IE-784000-R IE-784908-R-EM1 IE-784908-NS-EM1 EP-78064 SM78K4 System Simulator Windows Base SM78K Series System Simulator Reference External Part User Open Interface Specifications Reference Reference Document No. Japanese U11334J U11162J U11743J U11572J U11571J U11940J EEU-704 EEU-5008 U13356J U12903J U11876J U13743J EEU-934 U10093J U10092J English U11334E U11162E U11743E U11572E U11571E U11940E EEU-1291 U10540E U13356E U12903E -- On preparation EEU-1469 U10093E U10092E
ID78K4-NS Integrated Debugger PC Base ID78K4 Integrated Debugger Windows Base
U12796J U10440J U11960J
U12796E U10440E U11960E
ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS Base Reference
Caution The above documents may be revised without notice. Use the latest versions when you design application systems.
58
Data Sheet U11681EJ2V0DS00
PD78P4908
Documents Related to Software to Be Incorporated into the Product (User's Manual)
Document name 78K/IV Series Real-Time OS Fundamental Installation Debugger OS for 78K/IV Series MX78K4 Fundamental Document No. Japanese U10603J U10604J U10364J U11779J English U10603E U10604E -- --
Other Documents
Document name NEC IC Package Manual (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Device NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Guide to Quality Assurance for Semiconductor Devices Guide for Products Related to Microcomputer: Other Companies - C10535J C11531J C10983J C11892J -- U11416J Document No. Japanese English C13388E C10535E C11531E C10983E C11892E MEI-1202 --
Caution The above documents may be revised without notice. Use the latest versions when you design application systems.
Data Sheet U11681EJ2V0DS00
59
PD78P4908
[MEMO]
60
Data Sheet U11681EJ2V0DS00
PD78P4908
[MEMO]
Data Sheet U11681EJ2V0DS00
61
PD78P4908
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
62
Data Sheet U11681EJ2V0DS00
PD78P4908
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
Data Sheet U11681EJ2V0DS00
63
PD78P4908
IEBus is a trademark of NEC Corporation. MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT and PC DOS are trademarks of IBM Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of SONY Corporation. Some related documents may be preliminary versions. Note that, however, what documents are preliminary is not indicated in this document. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96. 5

▲Up To Search▲

Price & Availability of UPD78P4908

	To Download UPD78P4908 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .